1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming dummy pattern areas.
2. Description of the Related Art
Semiconductor devices are being made multi-layered in order to achieve a higher integration in a restricted area. Accordingly, as the integration degree of the semiconductor device becomes higher, a step difference becomes higher between a portion on which pattern areas are integrated and a portion on which pattern areas are isolated.
It is necessary to reduce the thickness of the pattern when a specific pattern is formed on an optional material layer in order to minimize the step difference. For this, the surface of a lower layer on which the pattern is formed is entirely flattened. The surface must be flattened to thin the pattern and to prevent the reduction of an over-etching margin according to the reduction of a design rule. For flattening the surface, a conventional technology provides a method for forming dummy pattern areas, i.e., conductor pattern areas which are not part of the operating circuits, on a wafer. The dummy pattern areas are formed in areas of a wafer in which the density of the pattern is relatively lower or in which no pattern is formed.
Methods for forming a dummy pattern areas according to the conventional technology is described with reference to attached FIGS. 1-5. With reference to FIG. 1, dummy pattern areas 14 are formed in an area on a substrate 10 in which conductive layer pattern areas 12a, 12b, and 12c are not formed, in the case that the conductive layer pattern areas 12a, 12b, and 12c on the substrate 10 pass over a lattice such as a gate array. The dummy pattern areas 14 are formed in the entire area so as to be aligned with a lattice.
According to this method, as shown in FIG. 4, a parasitic capacitor 30 is formed between a dummy pattern area 29 and an underlying conductive layer pattern area 26 in a lower layer, since an upper interlayer dielectric film 27 between the dummy pattern area 29 and the conductive layer pattern area 26 acts as a dielectric. Thus, the semiconductor device may misoperate. Another problem with this method is that it is hard to apply when the pattern of an underlying film is not regularly aligned.
With reference to FIG. 2, dummy pattern areas 18 are formed in the entire area in which conductive layer pattern areas 17a, 17b, and 17c on a substrate 16 are not formed. The dummy pattern areas 18 are not aligned in a lattice, but are formed as single bodies. A disadvantage of this method is that stress is concentrated on the dummy pattern area 18 since the dummy pattern area 18 is wider than the conductive layer pattern areas 17a, 17b, and 17c. As a result, cracks may be generated in the dummy pattern area 18 or in a conductive line formed below the dummy pattern 18. Further, as shown in FIG. 5, an upper interlayer dielectric film 27 between a wide dummy pattern area 31 and an underlying conductive layer pattern area 26 acts as a dielectric. Accordingly, a parasitic capacitor 32 between dummy pattern 31 and the conductive layer pattern 26 is formed and the semiconductor device may misoperate. In FIGS. 4 and 5, reference numeral 28 denotes a conductive layer pattern area and reference numeral 25 denotes a lower interlayer dielectric film.
Referring to FIG. 3, wide areas exist between the conductive layer pattern areas 21a, 21b, and 21c formed on the substrate 20. The bar-type dummy pattern area 22 is formed in the wide areas between the conductive layer pattern areas 21a, 21b, and 21c. A problem with this structure is that the semiconductor device may misoperate since a number of the parasitic capacitors are formed between the dummy pattern area 22 and conductive lines below.